AMD just announced the AMD Versal Premium Gen 2 Memory on Package, designed for engineers or companies with machines that need the space and power. Directly integrating memory into an adaptive SoC package enables faster data transfer, reduced latency, and lower power consumption compared to standard SoC packages.
Digging deeper into the architecture of the MoP, it integrates up to 32GB of LPDDR5X into a single package, delivering up to 288GB/s of bandwidth in up to 60% less board area. With this, system architects don’t have to worry about speed, space, and power trade-offs.
What It Unlocks For Systems
Versal Premium Gen 2 MoP devices integrate CXL 3.1 and PCIe 6.0 at 64Gb/s in hard IP, enabling high-speed data movement when paired with AMD EPYC CPUs to accelerate data-intensive applications. This provides greater flexibility for system architects to scale memory resources with LPDDR5X support of up to 9,000Mb/s and connectivity to CXL memory pooling and expansion modules.
As this chip is built for demanding, high performance systems, Versal Premium Gen 2 MoP adaptive SoCs support industrial-grade environments from -40 degrees Celsius to 110 C. This makes it ideal for systems that are important and always running, ensuring speed, space savings, as well as efficiency all at once.
Support Overview
AMD Versal Premium Gen 2 MoP devices offer 15-plus-year support. This allows systems to stay stable for longer, reduces the risk of sudden redesigns, and allows companies to plan for the future.
Regarding data protection, PCIe Integrity and Data Encryption (IDE), a feature introduced in PCIe 6.0, helps to protect data while it travels between parts of the chip. DDR memory encryption in integrated controllers protects that data while it’s stored in memory. Hard 400G High-Speed Crypto Engines enable high-bandwidth secure processing. Ultimately, strengthening security without sacrificing speed.
Versal Premium Gen 2 MoP devices include a pre-validated, in-package LPDDR5X interface that eliminates high-speed memory routing across the circuit board. This reduces board-level simulation and validation while helping shorten development cycles, lower design risk and minimize costly re-spins. Chip development is faster, cheaper, and less risky because engineers don’t have to redo their work as often.
Availability Timeline
Those interested or involved in the field can start building and testing with AMD’s current Versal Premium Gen 2 chips with AMD Vivado and Vitis tool workflows. Compatible IP and available reference designs helps existing customers to adopt new MoP devices and transition without learning everything again or changing their current setup.
MD Versal Premium Gen 2 MoP devices will start being tested at the end of 2026 with full mass production expected to begin in the second half of next year.
(Source: AMD)
