During the recent International Electron Devices Meeting (IEDM) at San Francisco in the US. TSMC, the Taiwanese semiconductor maker and fab, laid out its product roadmap for its semiconductors and next-gen process nodes. Among those plans, it listed out a goal of delivering multiple 3D-stacked chiplet designs, featuring at least one trillion transistors within a single chip package.
TSMC also spoke about how its plans to manufacture transistors within a 1nm die lithography by 2030 but it’ll move at regimented production speeds, with production expected to begin by the end of 2025. By 2028, it will move on to its 1.4nm A14 process, before ultimately reaching its fabled 1nm goals. For now, the manufacturer will continue to develop 2nm N2 and N2P nodes.
On a somewhat related note, TSMC and its CEO said in an earnings call that it is confident that its process nodes will leave Intel’s own nodes in the dust, even going so far as to say that it has “confirmed” that the enhancements of its N3P technology and that its 3nm class manufacturing node would perform far better than Intel’s own 18A node.
Unsurprisingly, Intel’s own Pat Gelsinger sort of took offense to that statement, even going so far as to retort that its 18A process node will outperform TSMC’s own 2nm die lithography, and that is even though the chipmaker will be launching its chips a year earlier.
(Source: Techspot)
