Aside from Radeon Instinct MI60 and Radeon Instinct MI50 accelerators which features 7nm Vega 20 GPU, AMD has also talked about the CPU side of business during the datacenter-oriented Next Horizon event in San Francisco earlier today. Specifically, the next generation CPU architecture that the company called Zen 2.
As per its name, Zen 2 is the successor to the original 14nm Zen architecture that the company introduced in 2015 before rolling out Zen-based products into the market starting from early 2017. While AMD did introduce the 12nm Zen+ architecture for consumer-oriented 2nd Gen Ryzen and Ryzen Threadripper processors, the next generation Epyc processor – codenamed “Rome” – will jump straight to the 7nm Zen 2 architecture.
By opting for 7nm process technology, it apparently allows AMD to double Zen 2’s chip density while cutting power consumption to half and achieve 25% more performance than its predecessor. Other than that, Zen 2 core also comes with improved execution pipeline, branch predictor, instruction pre-fetching, instruction cache, and op cache.
Other than that, the Zen 2 core’s floating point has also been doubled to 256-bit with similar improvement on its load/store bandwidth as well as increased dispatch/retire bandwidth. The Zen 2 core also carries several improved security features such as hardware-enhanced mitigations for Spectre and increased flexibility of memory encryption.
Altogether, these improvements apparently help Zen 2 core deliver up to twice the throughput as compared to the original Zen core. As opposed to the original Zen core which was first rolled out into the market via the consumer-oriented Ryzen CPUs, we were informed that Zen 2 will be first used to create datacenter product in the form of Epyc Rome processor that we mentioned earlier which is already being sampled by select AMD customers and will be released sometime in 2019.
For the time being, AMD has yet to reveal its plan on Zen 2-based consumer products but all in all, it is only a matter of time before that happens.
