At the start of the year, the PCI Special Interest Group (PCI-SIG) released an updated draft for the PCIe 7.0 specifications. Now, the group has released the final draft of the interface for member review, which also means that a final working product may be at hand.
“I am excited to share that PCI-SIG has released the PCI Express (PCIe) 7.0 specification, version 0.9 for member review. Version 0.9 is the final draft of the specification wherein members perform internal reviews of the technology for their essential patents. No additional functional changes are expected during this time, and we are on track to publish the full specification later this year. With this update, PCI-SIG is proud to continue our frequency of doubling the data rate every three years – from 64 GT/s of PCIe 6.0 specification to 128 GT/s raw bit rate.”
For those of you still wondering why we’re talking about PCIe 7.0 when the sixth generation of it has yet to reach the hands of the masses, two words: forward thinking. The initial use of these new interfaces isn’t generally designed for the consumer but rather, for datacentres and AI applications. As machine learning workloads become increasingly heavy and more demanding, so too does the need for speed and high-capacity data pipelines, as well as the need to eliminate bottlenecks between components.
Here’s a brief summary of the goals for PCIe 7.0, as per the PCI-SIG announcement:
- Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
- Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
- Focusing on the channel parameters and reach
- Improving power efficiency
- Continuing to deliver the low-latency and high-reliability targets
- Maintaining backwards compatibility with all previous generations of PCIe technology
(Source: PCI-SIG)
